There is technology which enlarges the adhesion area of a semiconductor chip and resin by making the outline dimension of a die pad smaller than the outline dimension of the semiconductor chip mounted on it, and enabling mounting of various semiconductor chips with differing outline dimensions on a die pad by cutting the tip of the lead to a proper length according to the outline dimension of the semiconductor chip (for example, refer to Patent Reference 1).
There is technology making it possible to choose the size of a semiconductor chip freely, without causing interference with a suspension lead by forming a half-cut section in a die pad, and doing the offsetting of the central part rather than the periphery in a QFN whose external terminal is projected below (for example, refer to Patent Reference 2).    [Patent Reference 1] Japanese patent laid-open No. Hei 6 (1994)-216303    [Patent Reference 2] Japanese patent laid-open No. 2000-243891